Pseudo-random frequency generator

ABSTRACT

A binary pseudo-random frequency generator in which a shift register is continuously strobed by a clock and has its informational content altered in accordance with its acquired state. A variable count divider counts down to zero from a number set therein from information received from the shift register at the divider zero count in response to frequency signals received from a voltage controlled oscillator. Divider zero counts are also compared in a phased lock loop with a reference frequency to set the voltage controlled oscillator frequency.

United States Patent Olmstead [451 Aug. 1, 1972 [54] PSEUDO-RANDOMFREQUENCY GENERATOR [72] Inventor: Merlin E. Olmstead, Baltimore, Md.

[73] Assignee: The Bendix Corporation [22] Filed: April 29, 1969 [21]Appl. No.: 820,230

[52] U.S. Cl. ..331/78, 178/22, 325/32, 325/122 51" rm. Cl. ..H03b 29 00[58] Field of Search ..33l/l, 78; 325/32-35, 122

[56] References Cited UNITED STATES PATENTS 3,484,712 12/1969 Foote eta1 ..331/1 Primary Examiner-Benjamin A. Borchelt Assistant Examiner-H.A. Birmiel Attorney-Flame, Arens, Hartz, Hi): and Smith, Bruce L. Lamb,William G. Christoforo and Lester L. Hallacher [57] ABSTRACT 17 Claims,1 Drawing Figure PSEUDO-RANDOM FREQUENCY GENERATOR BACKGROUND OF THEINVENTION The present invention relates to pseudo-random frequencygenerators and more particularly to pseudorandom frequency generatorswhich operate in accordance with digital principles.

It is often desirable when transmitting confidential messages over atransmission medium between remote stations to reduce the message at thetransmitting station to an unintelligible form before transmission andto reconstruct the message into the original form upon receipt at thereceiving station in order to prevent the message from being readilyunderstood if it is intercepted while in transit. Where the message hasbeen reduced to a conventional decodable electrical frequency at thetransmitting station, a degree of privacy can be accorded to the messageby translating the message frequency into a frequency band not normallyassociated with the type of message being transmitted and additionallyby constantly varying the translating frequency in accordance with apseudo-random schedule. To render the received message intelligible atthe receiving station, it is necessary to translate the receivedfrequency by the same amount but in an opposite direction as theoriginal frequency was translated at the transmitting station. Forexample, if a first portion of the original frequency is shifted upward500 hertz and a second portion of the original frequency is shiftedupward 1,000 hertz, then, at the receiving station, the first portion ofthe message must be shifted downward 500 hertz and the second portionshifted downward 1,000 hertz.

Frequency translation is accomplished by combining a message frequencywith the translating frequency in a mixer and filtering to choose thedesired sideband. If the desired sidebands are preselected by the systemdesigner by a suitable choice of filters, it is only necessary toprovide at both the transmitting and receiving stations simultaneously,identical translating frequencies which vary in a random like manner.

SUMMARY OF THE INVENTION It is an object of this invention to provide apseudorandom frequency generator employing digital techniques.

It is another object of this invention to provide a frequency generatorwhose output frequency varies in accordance with a predeterminedpseudo-random schedule.

Another object of this invention is to provide a pseudo-random frequencygenerator of the type described which can be easily reset to apredetermined initial state.

These and other objects of the invention which will become apparent froma reading of the following embodiment of the invention and claims areachieved by providing a digital shift register of predetermined lengthwhich changes state in a random-like manner so as to generate onselected output taps thereof a pseudorandom succession of binary numberswhich are gated into a variable count divider by a zero count signalgenerated when the divider attains a zero count. The variable countdivider is counted down by a voltage controlled oscillator whosefrequency is controlled in a phase locked loop wherein the zero countsignals are compared against a reference frequency. In this manner, thefrequency generated by the voltage controlled oscillator, which is thebasic output frequency of the device, will vary in a manner which isdetermined mainly by the binary numbers appearing on the output taps ofthe shift register, which, as has been mentioned, are varying in arandom-like but predictable manner. Thus, two or more identicalpseudo-random frequency generators of this type will track one another,that is, will provide identical frequency outputs simultaneously withone another, if their individual shift registers, variable countdividers and voltage controlled oscillators are reset simultaneously toidentical conditions.

More particularly, the shift register has its input supplied by a'modulo2 combination of certain shift register output taps. This shift registerarrangement has the capability of generating a cyclic code having arepetition period of 2"l bits. In the following preferred embodiment al6-stage shift register is shown together with one of over one hundredpossible four tap feedback positions that will give the full period of 2-1 bits.

BRIEF DESCRIPTION OF THE DRAWINGS The FIGURE is a block diagram of thepreferred embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the FIGURE, a shiftregister 10 composed in the conventional manner of 16 binary elements,suitably those binary elements commonly called flip-flops, 11 to 26, isstrobed by shift pulses generated by clock 8 which are applied to shiftregister shift pulse terminal 10b. Exclusive OR gates 30 and 31, whichare gates known in the art to generate a binary or two level output withtwo applied binary inputs such that like binary input levels producesone output binary level, while unlike binary input levels produces theother binary level, have their input terminals connected to samplepreselected output taps of shift register 10, for example, exclusive ORgate 30 has its input terminals connected to shift register output taps20a and 26a, while exclusive OR gate 31 has its input terminalsconnected to shift register output taps 14a and 17a. Output terminals30c and 31c of exclusive OR gates 30 and 31 respectively are connectedto input terminals 32a and 32b of exclusive OR gate 32, whose outputterminal 320 is connected through inverting amplifier 9 to flipflop 11input terminal 10a which comprises the shift register data inputterminal in the conventional manner.

Shift register output taps 12a, 14a, 18a, 21a and 25a are connected asinputs to coincident gates 35 to 39 respectively, which gates areconnected to receive a qualifying signal from coincident gate 65 vialine 65a. Output signals from gates 35 to 39 are used to set flipflops51 to 55 respectively, which comprise the five least significant bitelements of variable count divider 50, which is comprised of flip-flops51 to 60. Any output signal from coincident gate 65 is also applieddirectly to the set terminals of flip-flops 58 and 60 via line 65a.Variable count divider 50 is counted down by counting signals generatedby voltage controlled oscillator 45, these counting signals also beingapplied through inverting amplifier 47 to coincident gate 65 togetherwith variable count divider state signals from each of flip-flops 51 to60.

Phase detector 43, which together with voltage controlled oscillator 45,variable count divider 50 and coincident gate 65 comprise a phase lockedloop for controlling voltage controlled oscillator 45 output OPERATIONShift register 10 together with exclusive OR gates 30 to 32 comprise apseudo-random binary number generator in which a predetermined set ofnumbers will appear in accordance with a random-like schedule atselected shift register output terminals, for example, taps 12a, 14a,18a, 21a and 25a. Exclusive OR gates 30 to 32 are arranged so thatwhenever an odd number of shift register output taps 14a, 17a, 20a and26a, are energized, a logical 1 will be generated by gate 32 and isconnected to the inputs of flip-flop 11 so as to enter a logical intothe shift register with the next shift pulse. The shift registercontents are shifted in a normal manner by shift pulses generated byclock 8.

A selection of five of the outputs from among the 16 shift registerstages are applied to gates 35 to 39. Single outputs from these lattergates control the setting of the first five stages of -bit variablecount down binary divider 50. Fixed set connections are applied toflip-flops S8 and 60 by a signal on line 65a from coincident gate 65.Voltage controlled oscillator 45 generates an output frequency within apreselected frequency bank which is applied to counter 50, which thuscounts down to zero. The zero count is detected by coincident gate 65which is gated open by the oscillator 45 pulse as inverted by invertingamplifier 47. Output of gate 65 is applied along line 65a to set a countinto counter 50 at flip-flops 58 and 60 directly and through gates 35 to39 to flip-flops 51 to 55 respectively. The count entering through gates35 to 39 depend upon the instantaneous state of shift register 10 andmay be any number between 00000 and l l l l 1 (decimal 0 to 31).However, since numbers are preset into flip-flops 58 and 60 each timegate 65 opens, the minimum number which is set in counter 50 must bedecimal 640 when the number set through gates 35 to 39 is decimal 0 andthe maximum possible number set into the counter must be decimal 671when decimal 31 is entered into the counter through the gates.

The output of gate 65 is also applied to phase detector 43 which alsohas applied thereto a reference frequency from reference generator 42.The phase detector is designed to generate no error signal to vary thefrequency at voltage controlled oscillator 45 when its input frequenciesat inputs 43a and 4312 are equal, thus the output frequency of thevoltage controlled oscilla tor 45 must be equal to the referencefrequency generated by reference frequency generator 42 times the numberset into divider 50. Voltage controlled oscillator output frequency, aspreviously stated, is applied to count down variable count divider 50and is additionally tapped at terminal to comprise the pseudo-randomfrequency output of the device.

Through the use of suitable gating techniques, shift register 10,variable count divider 50 and voltage controlled oscillator 45 can bereset to a predetermined initial condition by a single reset pulseapplied to line in a manner well known to those skilled in the art. Ifthis reset pulse is applied simultaneously to two or more identicalpseudo-random frequency generators of the type herein described, theoutput frequencies of those generators so reset will track one another.

The invention claimed is:

1. Means for generating pseudo-random electrical frequencies comprising:

means for generating clock pulses;

a binary number generator having output taps, for generating upon saidoutput taps a random-like sequence of binary numbers in response to saidclock pulses;

binary means for counting electrical frequency signals;

means responsive to predetermined counts of said counting means forgenerating first electrical signals;

means responsive to said first electrical signals for entering a binarynumber related to an instantaneous one of said random-like sequence ofbinary numbers into said counting means; and,

a phase locked loop including said counting means and said firstelectrical signal generating means, for generating said pseudo-randomelectrical frequencies in response to said first electrical signals,said frequencies being counted by said counting means.

2. Frequency generating means as recited in claim 1 wherein said binarynumber generator comprises:

a shift register having a plurality of output taps, said random-likesequence of binary numbers appearing on preselected ones thereof, ashift pulse terminal to which said clock pulses are applied, and a datainput terminal; and,

gating means having input terminals connected to other preselected ofsaid output taps for applying a digital bit to said shift register datainput terminal.

3. Frequency generating means as recited in claim 2 wherein said shiftregister comprises a first cascade of binary elements connected as ashift register and said counting means comprises a second cascade ofbinary elements connected as a counter.

4. Frequency generating means as recited in claim 1 wherein said phaselocked loop comprises in addition to said counting means and said firstsignal generating means;

a source of reference frequencies;

a phase detector receiving as inputs said reference frequencies and saidfirst electrical signals for generating an error signal; and,

means responsive to said error signal for generating said pseudo-randomelectrical frequencies.

5. Frequency generating means as recited in claim I wherein said phaselocked loop comprises in addition to said counting means and said firstelectrical signal generating means:

a source of reference frequencies;

a phase detector responsive to said reference frequencies and said firstsignal for generating a voltage signals; and,

voltage controlled oscillator means responsive to said voltage signalfor generating said pseudo-random electrical frequencies.

6. Frequency generating means as recited in claim 5 with additionallymeans for resetting said voltage controlled oscillator, said binarynumber generator and said counting means to a predetermined initialstate.

7. Frequency generating means as recited in claim 5 wherein said voltagecontrolled oscillator means is constrained to generate electricalfrequencies within a predetermined frequency band.

8. Means for generating pseudo-random electrical frequencies comprising:

means for generating clock pulses;

a binary number generating means having output taps, for generating uponsaid output taps a random-like sequence of binary numbers in response tosaid clock pulses; and,

phase locked loop means for generating said pseudorandom electricalfrequencies in response to selected ones of said random-like sequence ofbinary numbers.

9. Means for generating pseudo-random electrical frequencies as recitedin claim 8 with additionally means for resetting said binary numbergenerating means and said phase locked loop means to a predeterminedinitial state.

l0. Means for generating pseudo-random electrical frequencies as recitedin claim 8 wherein said phase locked loop means comprises:

means for generating an error signal;

means responsive to said error signal for generating said pseudo-randomelectrical frequencies;

means for counting from a preset number to a predetermined number inresponse to said pseudorandom electrical frequencies;

means for generating an electrical signal upon said counting meansattaining said predetermined number, said means for generating an errorsignal being responsive to said electrical signal; and,

gating means responsive to said electrical signal for setting a numberrelated to one of said randomlike sequence of binary numbers into saidcounting means.

11. Means for generating pseudo-random electrical frequencies as recitedin claim 10 wherein said means for generating an error signal comprises:

a source of reference frequencies; and,

a phase detector responsive to said reference frequencies and saidelectrical signal for generating said error signal, said error signalcomprising a voltage level signal.

12. Means for generating pseudo-random electrical frequencies as recitedin claim 11 wherein said means for generating said pseudo-randomelectrical frequencies comprises a voltage controlled oscillatorcontrolled by said voltage level signal;

13. Means for generating pseudo-random electrical fre uencies recite inclai 0 herein said atin me ns compi'i ses a p urality ii dual mputCOlllCl enc gates, all said gates receiving as one input thereto saidelectrical signal and each said gate receiving as a second input theretothe binary bit appearing on one of said binary number generating meansoutput taps.

14. Means for generating pseudo-random electrical frequencies as recitedin claim 13 wherein said counting means comprises a cascade of binaryelements arranged to count from a preset binary number to apredetermined binary number in response to said pseudo-random electricalfrequencies, said preset binary number being preset into said countingmeans from said gating means.

15. Means for generating pseudo-random electrical frequencies as recitedin claim 14 wherein each said counting means binary element includes aset terminal and each of said plurality of dual input coincidence gatesis connected to a predetermined one of said set terminals.

16. Means for generating pseudo-random electrical frequencies as recitedin claim 15 wherein said gating means additionally comprises means forapplying said electrical signal directly to other of said set terminals.

17. Means for generating pseudo-random electrical frequencies as recitedin claim 16 with additionally means for resetting said voltagecontrolled oscillator, said counting means and said binary numbergenerating means to predetermined initial states.

1. Means for generating pseudo-random electrical frequencies coMprising:means for generating clock pulses; a binary number generator havingoutput taps, for generating upon said output taps a random-like sequenceof binary numbers in response to said clock pulses; binary means forcounting electrical frequency signals; means responsive to predeterminedcounts of said counting means for generating first electrical signals;means responsive to said first electrical signals for entering a binarynumber related to an instantaneous one of said randomlike sequence ofbinary numbers into said counting means; and, a phase locked loopincluding said counting means and said first electrical signalgenerating means, for generating said pseudorandom electricalfrequencies in response to said first electrical signals, saidfrequencies being counted by said counting means.
 2. Frequencygenerating means as recited in claim 1 wherein said binary numbergenerator comprises: a shift register having a plurality of output taps,said random-like sequence of binary numbers appearing on preselectedones thereof, a shift pulse terminal to which said clock pulses areapplied, and a data input terminal; and, gating means having inputterminals connected to other preselected of said output taps forapplying a digital bit to said shift register data input terminal. 3.Frequency generating means as recited in claim 2 wherein said shiftregister comprises a first cascade of binary elements connected as ashift register and said counting means comprises a second cascade ofbinary elements connected as a counter.
 4. Frequency generating means asrecited in claim 1 wherein said phase locked loop comprises in additionto said counting means and said first signal generating means; a sourceof reference frequencies; a phase detector receiving as inputs saidreference frequencies and said first electrical signals for generatingan error signal; and, means responsive to said error signal forgenerating said pseudo-random electrical frequencies.
 5. Frequencygenerating means as recited in claim 1 wherein said phase locked loopcomprises in addition to said counting means and said first electricalsignal generating means: a source of reference frequencies; a phasedetector responsive to said reference frequencies and said first signalfor generating a voltage signals; and, voltage controlled oscillatormeans responsive to said voltage signal for generating saidpseudo-random electrical frequencies.
 6. Frequency generating means asrecited in claim 5 with additionally means for resetting said voltagecontrolled oscillator, said binary number generator and said countingmeans to a predetermined initial state.
 7. Frequency generating means asrecited in claim 5 wherein said voltage controlled oscillator means isconstrained to generate electrical frequencies within a predeterminedfrequency band.
 8. Means for generating pseudo-random electricalfrequencies comprising: means for generating clock pulses; a binarynumber generating means having output taps, for generating upon saidoutput taps a random-like sequence of binary numbers in response to saidclock pulses; and, phase locked loop means for generating saidpseudo-random electrical frequencies in response to selected ones ofsaid random-like sequence of binary numbers.
 9. Means for generatingpseudo-random electrical frequencies as recited in claim 8 withadditionally means for resetting said binary number generating means andsaid phase locked loop means to a predetermined initial state.
 10. Meansfor generating pseudo-random electrical frequencies as recited in claim8 wherein said phase locked loop means comprises: means for generatingan error signal; means responsive to said error signal for generatingsaid pseudo-random electrical frequencies; means for counting from apreset number to a predetermined number in response to saidpseudo-random electrical frequencies; means for generating an elecTricalsignal upon said counting means attaining said predetermined number,said means for generating an error signal being responsive to saidelectrical signal; and, gating means responsive to said electricalsignal for setting a number related to one of said random-like sequenceof binary numbers into said counting means.
 11. Means for generatingpseudo-random electrical frequencies as recited in claim 10 wherein saidmeans for generating an error signal comprises: a source of referencefrequencies; and, a phase detector responsive to said referencefrequencies and said electrical signal for generating said error signal,said error signal comprising a voltage level signal.
 12. Means forgenerating pseudo-random electrical frequencies as recited in claim 11wherein said means for generating said pseudo-random electricalfrequencies comprises a voltage controlled oscillator controlled by saidvoltage level signal.
 13. Means for generating pseudo-random electricalfrequencies as recited in claim 10 wherein said gating means comprises aplurality of dual input coincidence gates, all said gates receiving asone input thereto said electrical signal and each said gate receiving asa second input thereto the binary bit appearing on one of said binarynumber generating means output taps.
 14. Means for generatingpseudo-random electrical frequencies as recited in claim 13 wherein saidcounting means comprises a cascade of binary elements arranged to countfrom a preset binary number to a predetermined binary number in responseto said pseudo-random electrical frequencies, said preset binary numberbeing preset into said counting means from said gating means.
 15. Meansfor generating pseudo-random electrical frequencies as recited in claim14 wherein each said counting means binary element includes a setterminal and each of said plurality of dual input coincidence gates isconnected to a predetermined one of said set terminals.
 16. Means forgenerating pseudo-random electrical frequencies as recited in claim 15wherein said gating means additionally comprises means for applying saidelectrical signal directly to other of said set terminals.
 17. Means forgenerating pseudo-random electrical frequencies as recited in claim 16with additionally means for resetting said voltage controlledoscillator, said counting means and said binary number generating meansto predetermined initial states.